Shattering the Memory Wall

Shattering the Memory Wall Stefano Giaconi

The First Fully Clockless Interconnect Ecosystem

About Us

Chronos Tech is US-based semiconductor IP design company developing game-changing IPs and fabric interconnect solutions to enable next-generation intelligent SoCs.
We target a wide range of applications-from cloud computing and AI to mobile and automotive-leveraging best-in-class latency and throughput performance for modern heterogeneous systems across multiple dies.

Technology Advantage

Best-in-class-performance and testability

Latency

  • 0.37 ns/mm
  • Lowest latency on the market
  • No clock penalties
  • PPA Calculator available for quick & accurate analysis

Throughput

  • 5GHz
  • Link speed not limited by distance
  • Support for wide data buses

Power

  • 0.1pJ/bit/mm
  • Low Power
  • Self clock–gating technology
  • Clock tree removal
  • Substantial saving with AVFS when combined with proprietary "O n Die Telemetry"

Hybrid-Bonding

  • Correct by construction
  • No MD-STA needed
  • Pre & Post Bonding integrated die level testing
  • No clock travelling across dies
  • Low Power

Routing Reduction

  • 50% (Based on a large mobile SoC)
  • Bus width reduction
  • Patented compression technology
  • Crosstalk mitigation

Area Reduction

  • 10% (Based on large SoC example)
  • Reduced top level routing -7%
  • Clock tree removal
  • Additional savings inside IPs

Testability

  • On Die Telemetry: on chip per-link performance measurement
  • Simplified margining and binning
  • Easier DPM analysis
  • Next Generation AVFS

Ease of Deployment

  • Deployable with standard Digital Flow and Tools
  • Soft IP
  • Automated generation of netlist and constraints
  • Automotive friendly
  • SoC protocol compatible (ARM, RISC-V, etc.)

Safe & Secure

  • Low EMI profile
  • Protect against Differential Power Analysis (DPA) attacks
  • Hardware Trojan detection
  • Soft Failure behavior

Design Space

Our solution covers a wide range of applications:

Cloud AI: Training / Inference

  • Best-in-class latency for accelerators
  • Unlimited scalability (Very large dies)
  • Reduces Latency in CXL Expanders
  • Easy integration of next generation Neuromorphic Processing Units (NPU) such as Spiking Neural Network (SNN)

Data Center / HPC

  • High Performance Interconnect
  • High Throughput Low Latency
  • Simplified pipelining and design closure
  • Ideal for CXL Expanders or High-Speed Switches
  • Unlimited Scalability (no clock limitations)

3D Interconnect ( Wormhole )

  • High Performance
  • PVT Resilient Interface (ideal for die to die)
  • Correct by construction (No MD-STA needed)
  • Low Power
  • Excellent test capability (pre- and post-Hybrid-Bonding)

Automotive / Mobile / Edge-Computing

  • Ideal for complex heterogeneous systems
  • Supports High Throughput
  • Low Latency, Safe and Secure
  • Built-in silicon self test and margining
  • Soft Failure behavior

Arm & RISC-V Based Solutions

  • SoC protocol compatible (AXI, ACE, CHI, Tilelink, OPB, etc.)
  • Tunable PPA per channel enables optimization & flexibility
  • Xplorer (GUI) provides early architectural investigation
  • Strong partnership within the Arm ecosystem